%0 Journal Article
%A Dongyao Zhai
%A Yue Lu
%A 段圣宇
%T <span class="fontstyle0">Statistical static timing analysis for circuit aging prediction</span>
%D 2021
%R 10.19682/j.cnki.1005-8885.2021.1002
%J 中国邮电高校学报（英文）
%P 14-23
%V 28
%N 2
%X <span class="fontstyle0">Complementary metal oxide semiconductor ( CMOS) aging mechanisms including bias temperature instability<br>
( BTI) pose growing concerns about circuit reliability. BTI results in threshold voltage increases on CMOS<br>
transistors, causing delay shifts and timing violations on logic circuits. The amount of degradation is dependent on<br>
the circuit workload, which increases the challenge for accurate BTI aging prediction at the design time. In this<br>
paper, a BTI prediction method for logic circuits based on statistical static timing analysis (SSTA) is proposed,<br>
especially considering the correlation between circuit workload and BTI degradation. It consists of a training phase,<br>
to discover the relationship between circuit scale and the required workload samples, and a prediction phase, to<br>
present the degradations under different workloads in Gaussian probability distributions. This method can predict<br>
the distribution of degradations with negligible errors, and identify 50% more BTI-critical paths in an affordable<br>
time, compared with conventional methods.</span> <br>
%U https://jcupt.bupt.edu.cn/CN/10.19682/j.cnki.1005-8885.2021.1002